A low-power 10-bit 0.01-to-12-MS/s asynchronous SAR ADC in 65-nm CMOS

Abstract During the last decades we have witnessed performance improvement and aggressive growth of complexity integrated circuits (ICs). The progressive size reduction transistors in recent technological nodes has allowed even compelled IC designers to perform analog tasks digital domain, increasing demand for analog-to-digital converters (ADCs). This work presents design implementation a low power, differential, asynchronous successive approximation register converter (SAR ADC) 65-nm CMOS technology. ADC works flexible range sampling rates, from few kS/s up 12.0 MS/s, being suitable application wide spectrum power systems subsystems, such as biosignal recorder interfaces frontend wireless receivers. At maximum rate, post-layout simulated circuit achieved an effective number bits (ENOB) 9.65 consumption 151.4 µW, leading Figure Merit 15.8 fJ/Conversion-step; at 10.0 ENOB is almost same, 9.63, but reduced only 0.26 µW. occupied area implemented 0.074 mm 2 .